DesignCon is part of the Informa Markets Division of Informa PLC
This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.
DesignCon is for Engineers, by Engineers
Throughout the year, DesignCon’s management consults with the electronics communities through its committees of distinguished engineers, industry leaders, and next-generation innovators. Their dedication and expertise help make DesignCon the nation's premier conference for chip, board, and systems design engineers.
Meet the Technical Program Committee
The DesignCon Technical Program Committee (TPC) is composed of approximately 100 leading experts in all levels of electronic design — chip, board, package, and system. These accomplished engineers and executives from top companies such as Siemens, Intel, Tektronix, Google, Apple, and Amazon Lab126 rigorously review all call-for-paper submissions to develop a conference of the highest quality and industry relevance. The TPC's dedication and expertise helps make DesignCon the nation's premier conference for chip, board, and systems design engineers.
Brice Achkir*, Cisco Fellow/VP Eng., Cisco Systems inc
Joseph Aday*, Senior Member of Technical Staff, Lockheed Martin
Maria Agoston*, Principal Engineer, Tektronix
Richard Allred, Senior Developer, MathWorks
John Andresakis, Director of Business Development, Ohmega/Ticer Technologies
Bruce Archambeault, retired
Pervez Aziz*, Senior Principal Engineer, Nvidia
Nitin Bhagwath, Principal Signal Integrity Engineer, Micron Technology
Rula Bakleh*, PMTS Silicon Design Engineer, AMD
Heidi Barnes*, SI/PI Applications Engineer, Keysight Technologies
Josiah Bartlett*, Principal Engineer in Asics and Technology Organization, Tektronix
Wendem Beyene*, Principal Engineer/Manager, Programmable Hardware Engineering, Intel
Gustavo Blando, Principal Hardware Engineer, Samtec
Luis Boluna, Sr. Applications Engineer, Keysight Technologies
Justin Butterfield, Principal Signal Integrity Engineer, Micron Technology
John Calvin, Senior Strategic Planner, Network and Data Center Infrastructure, Keysight Technologies
Robert Carter*, Vice President of Technology and Business Development, Oak-Mitsui Technologies
Chris Cheng*, Distinguished Technologist, HPE
David Choe, Product Engineering Director, Cadence
Antonio Ciccomancini Scogna*, Signal Integrity and EMC Technologist, Western Digital
Davi Correia, Sr Principal Application Engineer, Cadence Design Systems
Ben Dannan, Technical Fellow & Senior Staff Digital Engineer, Northrup Grumman
O.J. Danzy, Solution Engineering District Manager, Keysight Technologies
Jan De Geest, Senior Staff R&D Signal Integrity Engineer, Amphenol
Jay Diepenbrock, Consultant, SIRF Consultants
Vladimir Dmitriev-Zdorov, Principal Engineer, Siemens EDA
Greg Edlund, Senior Engineer, IBM
Jason Ellison*, Sr. Staff Signal Integrity Engineer, Amphenol
Shirin Farrahi, Senior Principal Software Engineer, Cadence
Paul Franzon, Cirrus Logic Distinguished Professor, Director of Graduate Programs, NCSU
Sanjeev Gupta*, Optical Network Engineer, Amazon Web Services (AWS)
Sunil Gupta, SIPI Technical Lead, Qualcomm Technologies, Inc.
Robert Haller*, Senior Principal Hardware Engineer, Extreme Networks
Gert Havermann, Signal Integrity Engineer, Harting
Allen F. Horn III*, Research Fellow, Rogers Corporation
Rockwell Hsu, Technical Leader, Cisco Systems
Seunghyun Hwang, Prinicpal Engineer, Nvidia
Joungho Kim, Professor, KAIST
Namhoon Kim, Chip Package Design Architect, Google
Billy Koo, Prinicpal Engineer, Samsung Electronics
Akhilesh Kumar, Principal R&D Engineer, Ansys
Amit Kumar, Principal Physical Design Engineer, Microsoft
Beomtaek Lee, Sr. Principal Engineer, Intel
Mike Li*, Fellow, Intel
Zhe Li, Hardware Engineer, Google
Cathy Liu*, Distinguished Engineer, Broadcom
Chris Loberg*, Marketing Manager, Tektronix
Om Mandhana, Staff Services AE, Cadence Design Systems
Marko Marin*, Technical Account Manager, ANSYS
Jon Martens, Fellow, Anritsu
Mehdi Mechaik*, Sr. Signal Integrity Engineer, Amazon Lab126
Richard Mellitz, Distinguished Engineer, Samtec
Ted Mido, Principal R&D Engineer, Synopsys
Akshay Mohan, EM Technology Lead, Amazon Lab126
Jose Moreira*, Senior Staff Engineer, Advantest
Zhen Mu*, Product Engineering Architect, Cadence
Riaz Naseer, Sr. Signal Integrity Engineer, Amazon Web Services (AWS)
Alfred P. Neves*, Chief Technologist, Wild River Technology
Istvan Novak*, Principal Signal and Power Integrity Engineer, Samtec
Vishram Pandit, Power Architect, Nvidia
Jongbae Park, System SI Architect, Apple
Pete Pupalaikis, Founding Member and Director of Signal Integrity, Nubis Communications
Kelvin Qiu, Senior Signal Integrity and Power Integrity Engineer, Google
Fangyi Rao, Master Engineer, Keysight Technologies
Lee Ritchey, President, Speeding Edge
Gerardo Romo-Luevano*, Sr. Staff Engineer/Manager, Qualcomm
Steve Sandler, Managing Director, Picotest
Venkat Satagopan*, Sr. Staff Signal Integrity Engineer, Nvidia
Christian Schuster, Professor, Hamburg University of Technology (TUHH)
Yan Fen Shen, Analog Engineer, Intel
Masashi Shimanouchi, Design Engineer, Intel
Yuriy Shlepnev, President, Simberian
Ben Silva, Analog Engineer, Intel
Bert Simonovich, President, Lamsim Enterprises
Chad Smutzer, Senior Engineer, Mayo Clinic
Mike Steinberger, Consulting Software Engineer, MathWorks
Suresh Subramaniam, Distinguished Engineer, Apex Semiconductor
Madhavan Swaminathan, Department Head and William E. Leonhard Professor, Penn State, College of Engineering
Donald Telian, Owner / Consultant, SiGuys
Lars Thon*, Consultant, LT Engineering
Thomas To*, Director, AMD
Peter Tomaszewski, Sr. Digital Solutions Engineer, Keysight Technologies
Ambrish Varma*, Sr Principal Software Engineer, Cadence
Harald von Sosen, Principal Engineer, Siemens EDA
Juan Wang, Senior Staff Engineer, AMD
Scott Wedge, Principal Engineer, Siemens EDA
Hubert Werkmann, Consulting Director, Advantest
Todd Westerhoff, Product Marketing Manager, Siemens EDA
Markus Witte, Systems Engineer, GRIMME
Randy Wolff, Product Architect , Siemens EDA
Hsinho Wu*, Design Engineer, Intel
Ken Wu, Principal MTS, Package and SI/PI Lead, Rivos
Chris Wyland*, Principal Engineer - AVP R&D Electrical Simulation , Samsung Semiconductors
Kai Xiao, Principal Engineer, Intel Corporation
Zhiping Yang, Adjunct Professor , Missouri University of Science and Technology
Mobashar Yazdani*, Strategic Semiconductor Manager, Google
Iliya Zamek, Architect, Technical Manager, HCL America
Geoffrey Zhang, Distinguished Engineer and Supervisor , AMD
Pavel Zivny, Domain Expert, Tektronix
*2025 track co-chair
Copyright © 2024. All rights reserved. Informa Markets, a trading division of Informa PLC.